The present invention relates to a process for fabricating a non-volatile memory cell having a floating gate region self-aligned to the insulator, and having a high coefficient of coupling. The present invention relates more particularly, but not exclusively, to a process for fabricating a nonvolatile EPROM or flash EPROM cell.
As is well known, EPROM or flash EPROM type electronic memory devices are integrated in a semiconductor material and comprise a plurality of non-volatile memory cells arranged in a matrix array. The non-volatile memory cells each comprises a MOS transistor having a gate region located above the channel region which is floating, i.e., it has a high DC impedance to all the other terminals of the cell and the circuit wherein the cell is incorporated. The cell also has a second region, known as the control gate, which is driven by suitable control voltages. The other electrodes of the transistor are the standard drain, source, and body terminals.
There has been considerable effort in the last few years to develop memory devices with ever higher rates of circuit density. A continuing miniaturization of the cell, essential to an increased integration density, has led to a substantial reduction in the characteristic parameters of non-volatile memory cells, e.g., in the area occupied by the elementary unit that is repeated to make up the array.
Area occupation is defined as the product of the y-pitch and x-pitch (see FIG. 1), i.e., the cell dimensions along respective y and x directions in a horizontal plane. For a memory cell, e.g., of the conventional NOR type used in EPROM and flash type memories, the y-pitch dimension is given by the sum of the cell half-contact dimension, the distance from the contact to the gate region, the length dimension of the gate region and the half-sourceline.
The x-pitch dimension is given by the width of the memory cell active area, or the dimension of the floating gate region, plus the respective distance. Limiting factors to a reduction of the x-pitch dimension are the resolution of the fabricating process and, therefore, in defining the floating gate region, the alignment tolerances of the floating gate region to the active area.
A recent Toshiba publication (K. Imamiya et al., xe2x80x9cA 130 mm 256 Mb NAND Flash with Shallow Trench Isolation Technologyxe2x80x9d, MP 6.6, IEEE ISSCC, 1999) describes a memory cell having its floating gate region self-aligned to the isolation layers. Although advantageous on several counts, this approach has some drawbacks. In fact, it does not solve the problem of providing a good capacitive coupling between the control gate and the floating gate region. The coupling could be improved by extending the floating gate region to overlie the layer of field oxide that surrounds the active area of the cell along the x direction. However, several polysilicon layers would have to be aligned to the active area to achieve such an improved capacitive coupling. This structure formation adds problems of alignment and photolithography tolerance to the process steps.
In view of the foregoing background, an object of the present invention is to provide a memory device and process for fabricating a non-volatile memory cell of the memory device, whereby a floating gate region can be obtained which is self-aligned to the active area of the cell, and whereby the coupling area between the floating gate region and the control gate region can be enhanced. Accordingly, this process should have appropriate structural characteristics to overcome the limitations and drawbacks of the prior art.
This and other objects, advantages and features in accordance with the present invention are provided by a floating gate region formed by a double deposition of polycrystalline silicon (polysilicon), wherein the first deposition allows the floating gate region to be self-aligned to the active area, while the second deposition allows the surface of the floating gate region to be extended as much as possible in the x direction of the cell without presenting lithography alignment problems.
More particularly, the invention is directed to a memory device or integrated circuit that may include a floating gate defined by a stacked structure comprising a first dielectric layer, and a first conducting layer isolated from the substrate by the first dielectric layer, at least one trench in the substrate adjacent the floating gate, and a second dielectric layer in the at least one trench. Moreover, the memory device may also include conductive extensions contacting the first conducting layer of the floating gate and extending laterally outwardly therefrom over adjacent portions of the second dielectric layer. The conductive extensions may have upper surface portions being substantially coplanar with adjacent upper surface portions of the first conducting layer of the floating gate. In addition, the conductive extensions may have a thickness substantially equal to a thickness of the first conducting layer of the floating gate.
The conductive extensions may each comprise a second conducting layer, and the first and second conducting layers may each comprise polysilicon. The first and second dielectric layers may each comprises silicon oxide. The at least one trench may have sloping sidewalls, having, for example, a slope angle in a range of about 60 to 90 degrees with respect to the substrate.